1. Field of the Invention
The present invention generally relates to a semiconductor package structures, and more specifically, to a chip scale package structure and a method for fabricating the same.
2. Description of Related Art
Along with the advancement of the semiconductor technology, semiconductor products have been developed in a variety of different package types. In the pursuing of a lighter, thinner and smaller semiconductor package structure, a chip scale package (CSP) structure has been developed. The feature of this chip scale package structure is that its size is equal to or a little bit bigger than the chip size.
U.S. Pat. Nos. 5,892,179, 6,103,552, 6,287,893, 6,350,668, and 6,433,427 disclose a conventional CSP structure, which applies build-up layers directly on the top of the chip without using a chip carrier such as a substrate or a lead frame, and by means of the redistribution layer (RDL) technology to redistribute the bond pads of the chip to the intended positions. As shown in FIG. 1, this CSP structure has a build-up layer formed on an active surface 100 of a chip 10. The build-up layer comprises a dielectric layer 11 applied on the active surface 100 of the chip 10 and provided with a plurality of through holes 110 for exposing a plurality of bond pads 101 disposed on the chip 10, and a circuit layer 12 formed on the dielectric layer 11 and electrically connected to the exposed bond pads 101. A solder mask 13 is further applied on the circuit layer 12. The solder mask 13 is provided with a plurality of openings 130 for exposing a predetermined part of the circuit layer 12, allowing the predetermined part to be electrically connected to a plurality of solder balls 14, which are used as the input/output ends for electrical connections to external electronic devices.
However, the disadvantage of the aforementioned CSP structure is that the application of the redistribution technology or the distribution of the conductive traces on the chip is always restricted by the size of the chip or its active surface area, especially in the situation that the chip integration level is getting higher and the chip size is getting smaller, the chip can not even provide enough or more surface for installing higher number of solder balls for effectively electrically connecting to external devices.
In view of the aforementioned drawback, U.S. Pat. No. 6,271,469 discloses another package structure that forms a build-up layer on the chip, which provides more surface area to carry more input/output ends or solder balls. As shown in FIG. 2, a package structure uses an encapsulant 25 to encapsulate an inactive surface 202 and a lateral 203 of a chip 20, but leaves an active surface 200 of the chip 20 be exposed. The active surface 200 is at the same level as a surface 250 of the encapsulant 25. A first dielectric layer 26 is applied on the active layer 200 of the chip 20 and the surface 250 of the encapsulant 25. The first dielectric layer 26 is provided with a plurality of through holes 260 made by a laser drilling technique. A first circuit layer 22 is applied on the first dielectric layer 26 and electrically connected to exposed bond pads 201. A second dielectric layer 27 is applied on first circuit layer 22 and is provided with a plurality of through holes 270 for exposing a predetermined part of the first circuit layer 22. A second circuit layer 28 is formed on the second dielectric layer 27 and electrically connected to the exposed predetermined part of the first circuit layer 22. A solder mask 23 is applied on the second circuit layer 28 and is provided with a plurality of predetermined part of the second circuit layer 28, allowing the predetermined part of the second circuit layer 28 to be electrically connected to a plurality of solder balls 24. Therefore, the surface 250 of the encapsulant 25 that encapsulates the chip 20 provides a surface area larger than that the active surface 200 of the chip 20 can provide for installing more solder balls 24 to effectively electrically connect to external devices.
However, the package structure of the aforementioned disclosure has its drawback, when open the plurality of via holes that go through the first dielectric layer to expose the bond pads of the chip by means of laser drilling technology, the plurality of bond pads of the chip are covered by the first dielectric layer, generally it is difficult to aim the laser beam accurately at the solder pad position, consequently the via holes opened can not be aligned accurately to the corresponding bond pad position; since the bond pads of the chip can not completely exposed, it is difficult to ensure the electricity connection quality between the circuit layer and the bond pads, thereby hurting the yield and reliability of the finished products. Meanwhile, the applying of the first dielectric layer on the tops of the chip and the encapsulant as well as the application of the laser drilling technology increase the production cost and fabrication complexity, and the first dielectric layer has different coefficient of thermal expansion (CTE) from the chip and the encapsulant, in a high temperature environment or a heat circulation situation, the first dielectric layer will produce different thermal stress from the chip and the encapsulant and consequently the interface between them will delaminate, thereby leveling down the quality and reliability of the finished products.
Please further refer to FIGS. 3A through 3D. To overcome the aforementioned drawbacks, a CSP structure and its fabrication method is disclosed according to U.S. Pat. No. 7,002,245, wherein, as shown in FIG. 3A, first preparing a wafer that has a plurality of chips, an active surface of each chip 30 having a plurality of bond pads 301. Then forming a conductive bump 31 on each of the bond pads 301, cutting the wafer into a plurality of chips, each of which has a plurality of conductive bump 31. As shown in FIG. 3B, attaching each chip 30 on an adhesion tape 36 via its conductive bumps, and then forming an encapsulant 35 that encapsulates the chips 30 and the conductive bumps 31. As shown in FIG. 3C, removing the adhesion tape 36 to have the end of each conductive bump 31 be uncovered from the encapsulant 35 and be on the same level as one surface of the encapsulant 35, and then forming a plurality of conductive traces 32 on the surface of the encapsulant 35 and electrically connected the conductive traces 32 to the uncovered ends of the conductive bumps 31. As shown in FIG. 3D, applying a solder mask on the conductive traces 32, and then uncovering a plurality of predetermined parts of the conductive traces 32 from the solder mask 33 for mounting a plurality of solder balls 34. Lastly, cutting the encapsulant 35 to form a plurality of semiconductor packages of single isolated chip.
However, the aforementioned fabrication method of CSP structure is using a batch-type method to attach a plurality of chips, which have conductive bumps, on an adhesion tape in an array layout, thus it is difficult to accurately control the relative attach position for each chip due to the machine inaccuracy or other factors, namely, it can not accurately control the positions of the ends of the conductive bumps of the chip uncovered from the encapsulant, meanwhile, the attach positions of the plurality of chips on an adhesion tape is different from the corresponding attach positions of the plurality of chips on another adhesion tape, therefore, it can not accurately align the relative positions between one another, thus in the subsequent process of removing the adhesion tape and patterning process that forms the conductive traces on the top of encapsulant for electrically connecting to the uncovered ends of the conductive bumps, it must go through each individual step of exposing and developing for each batch of the plurality of chips, therefore, it increases the production cost, and practically it can not effectively process mass production.
Hence, it is a highly urgent issue in the industry for how to provide a chip scale package structure and its fabrication method which is capable of ensuring the electricity connection quality between the circuit layer and the bond pads, enhancing the yield and the reliability of the finished products, and meanwhile decreasing the production cost and simplifying the fabrication process.